Integrated circuit (IC) is one of the most common components for electric products in our daily lives. To increase the number of the logic gates or circuits in a unit area/volume is a consistent goal for IC engineers. 3D IC integration has many advantages compared to normal encapsulation process, such as smaller component size, less signal loss, and better electrical performance.
Wafer thinning is one of the key techniques to develop 3D IC integration, and the wafer can be thinned under 100 micrometers by current technology. Generally, the manufacturing process is exposing the through-silicon via (TSV) of the thinned wafer and executing the following processes, such as circuit redistribution on the back, removing the bond (stripping) of the carrier, and finishing the fabrication of the medium layer. However, the disadvantage of the current method for wafer thinning is that it is easy to damage the carrier when removing the bond and the step of thinning is very complex. Therefore, the current yield rate of wafer thinning is not ideal and the cost is amazing.